AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs

arXiv:2403.10686v1 Announce Type: cross
Abstract: High-level synthesis (HLS) is a design flow that leverages modern language features and flexibility, such as complex data structures, inheritance, templates, etc., to prototype hardware designs rapidly. However, exploring various design space parameters can take much time and effort for hardware engineers to meet specific design specifications. This paper proposes a novel framework called AutoHLS, which integrates a deep neural network (DNN) with Bayesian optimization (BO) to accelerate HLS hardware design optimization. Our tool focuses …

abstract arxiv cs.ai cs.ar cs.lg data design designs engineers etc exploration features flexibility flow hardware however inheritance language modern parameters space synthesis type