Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout

arXiv:2404.17701v1 Announce Type: cross
Abstract: Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology …

abstract application array arxiv cmos cs.ar cs.lg design efficiency embedded fpga gate implementation logic low low power machine machine learning particle physics.ins-det power reconfigurable technology type