NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions

arXiv:2403.00849v1 Announce Type: cross
Abstract: Field-Programmable Gate Array (FPGA) accelerators have proven successful in handling latency- and resource-critical deep neural network (DNN) inference tasks. Among the most computationally intensive operations in a neural network (NN) is the dot product between the feature and weight vectors. Thus, some previous FPGA acceleration works have proposed mapping neurons with quantized inputs and outputs directly to lookup tables (LUTs) for hardware implementation. In these works, the boundaries of the neurons coincide with the boundaries …

abstract accelerators array arxiv cs.ar cs.lg deep neural network dnn feature field-programmable gate array fpga functions gate inference latency network neural network operations product stat.ml tasks type vectors