DE-HNN: An effective neural model for Circuit Netlist representation

arXiv:2404.00477v1 Announce Type: new
Abstract: The run-time for optimization tools used in chip design has grown with the complexity of designs to the point where it can take several days to go through one design cycle which has become a bottleneck. Designers want fast tools that can quickly give feedback on a design. Using the input and output data of the tools from past designs, one can attempt to build a machine learning model that predicts the outcome of a …

arxiv cs.ar cs.lg representation type