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Self-Learning Tuning for Post-Silicon Validation. (arXiv:2111.08995v3 [cs.LG] UPDATED)
cs.LG updates on arXiv.org arxiv.org
Increasing complexity of modern chips makes design validation more difficult.
Existing approaches are not able anymore to cope with the complexity of tasks
such as robust performance tuning in post-silicon validation. Therefore, we
propose a novel approach based on learn-to-optimize and reinforcement learning
in order to solve complex and mixed-type tuning tasks in a efficient and robust